![]() I am providing the code kindly help me finding the problem. The ring counter is working fine but the Parallel to serial converter is not working properly and I am getting x undefined result. And I don't know how to model that proprely. I am making a parallel to serial converter using ring counter in verilog. ![]() But my final waveform look like this: Here is my code, thanks in advance. generate but I need to use that i as index.ĭoes anyone know how to fix my code? The main issue is that using serial input, the flipflop are connected in series while parallel input, the flipflops are independent. I'm trying to design a parallel to serial converter. I was thinking to use for loop instead of for i. For the simulation, the Parallel to serial converter is used to generate data and the. The received data is available in parallel format on the dataout bus. If a framein signal is detected, the data is latched in and the datardy output is asserted until the rd input is asserted by the host. ![]() ![]() My issue is that I need to use a If statement to choose my input (parallel or serial) (which must be inside a process) and I also need a for generate statement because I work with generic n bit register (which cannot be done inside a process) to build the n D-Flipflop. This VHDL module receives serial data from the datain line.The data is continuously shifted in. I want to build a n bits register which can take both serial or parallel input depending of a bit SERIAL. The VHDL source code for a parallel multiplier, using generate to make the VHDL source code small is mul32c.vhdl. ![]()
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December 2022
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